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Design Engineer – Power Management ICs

The Hong Kong University of Science and Technology · Tai Po District

Mid 🇬🇧 English
SPICE Verilog SystemVerilog EDA tools RTL design simulation DRC LVS

Job description

About the role

As a member of the IC design team at PowerSAC, you will help develop power‑management integrated circuits from concept through silicon validation and product release. You will work on applications such as DC‑DC converters, LDOs, gate drivers, battery‑management and digitally assisted power control.

Key responsibilities

  • Define product and block specifications, perform circuit architecture studies and system‑level analysis.
  • Design and simulate analog, digital or mixed‑signal blocks (e.g., amplifiers, bias circuits, switches, LDOs, ADC/DAC, digital control).
  • Carry out transistor‑level or RTL design and verification using appropriate simulation and sign‑off flows.
  • Support mixed‑signal block integration and collaborate with analog, digital and verification engineers.
  • Work with layout engineers on floor‑planning, device matching, parasitic review, DRC/LVS closure and post‑layout simulation.
  • Optimize designs for performance, power, area, robustness and manufacturability.
  • Prepare documentation, present results in design reviews and track issues to closure.
  • Perform hands‑on IC evaluation, debugging and support test development in the laboratory.

Required profile

  • Master’s degree in Electrical Engineering, Microelectronics or a related field.
  • At least 2 years of relevant IC design experience.
  • Strong fundamentals in at least one area: analog, digital or mixed‑signal design.
  • Ability to learn quickly, work carefully with guidance and take ownership of assigned blocks.

Required skills

  • SPICE‑based circuit simulation.
  • Verilog / SystemVerilog for digital design and verification.
  • Experience with industry‑standard EDA tools and design flows.
  • Transistor‑level or RTL design and verification.
  • Corner‑analysis, sign‑off flows, DRC/LVS closure.
  • Post‑layout simulation and understanding of CMOS device behavior.

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Published 3 weeks ago

Expires 1 month from now

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The Hong Kong University of Science and Technology

Tai Po District