Senior Analog Power Management Designer

About the role

Lead the architecture, design, and development of next‑generation Power Management Integrated Circuits (PMIC). Own the full product lifecycle from specification through silicon bring‑up to mass‑production support. Drive technical innovation and mentor junior engineers.

Key responsibilities

• Lead product specification definition, architecture selection, and process node evaluation for new PMIC families.
• Architect and implement critical circuit blocks from transistor level to system level, ensuring robustness across PVT corners.
• Define verification strategy, simulation plans, and corner‑case methodologies to guarantee first‑pass silicon success.
• Direct physical layout implementation with strict matching, symmetry, and parasitic control.
• Lead silicon bring‑up, characterization, root‑cause analysis, and performance optimization.
• Collaborate with test and product engineers to develop production test plans and drive yield improvement.
• Propose novel circuit ideas, create IP, and file patents.
• Author application notes, guidelines, and data sheets.

Required profile

• Master's or Ph.D. in Electrical Engineering or Microelectronics.
• 5+ years of proven experience in Power Management IC design (analog/mixed‑signal).
• Track record of taking multiple chips from concept to high‑volume mass production.
• Strong problem‑solving ability for complex silicon issues.
• Excellent communication and cross‑functional leadership skills.
• Ability to manage time and deliver projects as a design lead.

Required skills

• Analog and mixed‑signal IC design.
• Power management topologies, control loops, and stability analysis.
• Semiconductor physics and IC design flows.
• Expertise with industry‑standard EDA tools.
• Scripting/automation for design tasks.